This invention relates to a method of manufacturing a metal-insulator-semiconductor (MIS) field-effect transistor that is fabricated on a silicon carbide substrate in which the crystal surface orientation of the substrate is prescribed and the impurity diffusion layer is optimized, particularly to a method of manufacturing a semiconductor device in which the method of forming a gate insulation layer and the following heat treatment are contrived.
A number of inventions have already been disclosed relating to a method of oxidizing a silicon carbide substrate and the following heat treatment method, and to an MIS field-effect transistor having a buried channel region.
For example, U.S. Pat. No. 5,864,157 describes a structure that, in a flash memory having dual gates, uses a P-type electrode for the lower gate and an N-type impurity for the buried channel region. However, this description relates to a flash memory having dual gates, which is different from the structure of the present invention. Also, there is no description concerning the concentration of the P-type polysilicon electrode and the impurity concentration of the buried channel region, and the relationship between the depth of the source region or drain region and the depth of the channel region.
In JP-A HEI 8-186179, there is described a structure, in an N-channel transistor having an LDD structure, that uses a P-type electrode for the gate electrode and an N-type impurity for the buried channel region. However, in this JP-A HEI 8-186179, there is no description concerning the impurity concentration of the P-type polysilicon electrode and the relationship between the depth of the source region or drain region and the depth of the channel region.
Also, JP-A HEI 7-131016 describes an MIS field-effect transistor structure characterized by the transistor channel formation surface being parallel to the (1, 1, xe2x88x922, 0) surface of the hexagonal silicon carbide single-crystal substrate. However, this JP-A HEI 7-131016 does not describe anything relating to a buried channel region type MIS field-effect transistor that uses a P-type electrode for the gate electrode.
With respect to a method of oxidizing a silicon-carbide substrate, U.S. Pat. No. 5,972,801 describes a method that, following formation of the gate oxide layer, includes exposing the gate oxide layer to an atmosphere containing water vapor at a temperature of 600xc2x0 C. to 1000xc2x0 C., but this process is carried out under conditions whereby there is no increase in the thickness of the gate oxide layer of the silicon carbide substrate that is thus further oxidized. This differs from the present invention, in that in the present invention, the silicon carbide substrate is slightly oxidized and the thickness of the gate oxide layer is increased.
JP-A HEI 5-129596 discloses a process for dry oxidation and wet oxidation of a silicon substrate. From the description, this is a process that increases the gate layer thickness by using wet oxidation to oxidize a semiconductor substrate, as understood from the description, xe2x80x9c(A) is when dry oxidation is performed for 85 minutes, making the thickness of the gate oxide layer 25.3 nm, and (B) is when, similarly, dry oxidation is performed for 80 minutes, after which wet oxidation is performed for 1 minute, making the thickness of the gate oxide layer 26.3 nm.xe2x80x9d
However, this JP-A HEI 5-129596 shows no disclosure relating to the composition of a buried channel type MIS field-effect transistor. It is known that in this type of transistor, the performance is highly dependent on the profile of the diffused impurity. Therefore, the relationship between the heat treatment in the oxidizing process and the introduction of the impurity is important. With respect to the impurity that is introduced, because the present invention uses a silicon carbide substrate having a diffusion coefficient that is lower than that of a silicon substrate, it is possible to use heat treatment for the purpose of oxidation, after forming the diffusion layer used for the buried channel, and the source/drain diffusion layer. The present invention differs from the invention of the JP-A HEI 5-129596 in that it discloses a process that allows the use of a silicon carbide substrate.
Compared to a silicon MIS transistor, the interfacial level density of an oxide layer-silicon oxide interface using a silicon carbide substrate generally is approximately one order of magnitude higher. Therefore, an MIS field-effect transistor that uses a silicon carbide substrate has a problem that channel mobility is approximately one order of magnitude lower than that of an MIS field-effect transistor that uses a silicon substrate. In the case of a silicon MIS transistor, it is known that a buried channel region type MIS field-effect transistor is superior because the flow of electrons from the source to the drain is not readily affected by the above interface between oxide layer and silicon carbide. But, when a silicon MIS transistor on a silicon carbide substrate is made as a buried channel region type structure that is not optimized, it readily becomes normally on (a phenomenon where current flows between source and drain even when the gate voltage is zero). Also, in cases where optimization is not attempted, hot carrier resistance is poor and adequate punch-through resistance cannot be achieved.
This invention was proposed in consideration of the above and, in a semiconductor device using a silicon carbide substrate, has as its object to provide a method of manufacturing a semiconductor device that is a buried channel region type transistor that by optimizing the structure of the burned channel region type MIS transistor, gate insulation layer formation method and surface orientation of the silicon carbide substrate, does not become normally on and, moreover, has high hot-carrier resistance, high punch-through resistance and high channel mobility.
For achieving this object, a first aspect of the present invention relates to a method of manufacturing a semiconductor device characterized by including a step of forming a buried channel region, a source region and a drain region, a step of forming a gate insulation layer after the step of forming the buried channel region, source region and drain region, and a step of exposing the gate insulation layer to an atmosphere containing water vapor at a temperature of 500xc2x0 C. or more after the step of forming the gate insulation layer in a semiconductor device characterized by having a semiconductor substrate that forms a P-type silicon carbide region, a gate insulation layer formed on the P-type region, a gate electrode that exhibits P-type characteristics formed on the gate insulation layer, an N-type impurity region having an adequate impurity concentration for forming a buried channel region in a semiconductor layer below the gate insulation layer, and transistor-constituting source and drain regions each composed of an N-type impurity region formed respectively adjacent to the gate insulation layer and the gate electrode.
In order to achieve a high mobility by optimizing a formation depth of the buried channel region and improve the step of forming the gate insulation layer, in addition to the first aspect, a second aspect of the present invention is characterized by including a step of forming a buried channel region, a source region and a drain region, a step of forming a gate insulation layer after the step of forming the buried channel region, source region and drain region, and a step of exposing the gate insulation layer to an atmosphere containing water vapor at a temperature of 500xc2x0 C. or more after the step of forming the gate insulation layer in the semiconductor device described in claim 1 that comprises a semiconductor device in which a ratio (Lbc÷Xj) between junction depth (Lbc) of the buried channel region from an interface between the gate insulation layer and the silicon carbide region, and depth (Xj) of a junction portion of the source and drain regions from the interface between the gate insulation layer and the silicon carbide region is within a range of not less than 0.2 and not more than 1.0.
In addition to the first or second aspect, a third aspect of the present invention is characterized by including a step of forming a buried channel region and a source region and a drain region, a step of forming a gate insulation layer after the step of forming the buried channel region, source region and drain region, and a step of exposing the gate insulation layer to an atmosphere containing water vapor at a temperature of 500xc2x0 C. or more after the step of forming the gate insulation layer in the semiconductor device that is polycrystalline silicon in which boron is diffused and which has an impurity concentration within a range of 1xc3x971016 cmxe2x88x923 to 1xc3x971021 cmxe2x88x923.
In addition to the first or second aspect, a fourth aspect of the present invention that relates to a buried channel region is characterized by including a step of forming the buried channel region a source region and a drain region, a step of forming a gate insulation layer after the step of forming the buried channel region, source region and drain region, and a step of exposing the gate insulation layer to an atmosphere containing water vapor at a temperature of 500xc2x0 C. or more after the step of forming the gate insulation layer in the semiconductor device in which the buried channel region has diffused therein a nitrogen, phosphorus or arsenic impurity having a maximum concentration of 5xc3x971015 cmxe2x88x923 to 1xc3x971018 cmxe2x88x923.
In addition to any of the above first to fourth aspects, a fifth aspect of the present invention that relates to lowering resistance of a gate electrode is characterized by including a step of forming a buried channel region, a source region and a drain region, a step of forming a gate insulation layer after the step of forming the buried channel region, source region and drain region, and a step of exposing the gate insulation layer to an atmosphere containing water vapor at a temperature of 500xc2x0 C. or more after the step of forming the gate insulation layer in the semiconductor device in which the gate electrode includes a high-melting-point metal silicide layer.
In addition to the fifth aspect, a sixth aspect of the present invention is characterized by including a step of forming a buried channel region, a source region and a drain region, a step of forming a gate insulation layer after the step of forming the buried channel region, source region and drain region, and a step of exposing the gate insulation layer to an atmosphere containing water vapor at a temperature of 500xc2x0 C. or more after the step of forming the gate insulation layer in the semiconductor device in which the high-melting-point metal silicide layer is a tungsten, molybdenum or titanium silicide layer.
In addition to any of the above first to sixth aspects, a seventh aspect of the present invention that relates to a hot-carrier resistance improvement technology is characterized by including a step of forming a buried channel region, a source region and a drain region, a step of forming a gate insulation layer after the step of forming the buried channel region, source region and drain region, and a step of exposing the gate insulation layer to an atmosphere containing water vapor at a temperature of 500xc2x0 C. or more after the step of forming the gate insulation layer in the semiconductor device that has a region between a region in which the buried channel region is formed and the source or drain region having an impurity concentration that is not lower than a maximum impurity concentration of an impurity diffusion layer region used to form the buried channel region, and not higher than an impurity concentration of the source or drain region.
In addition to the above seventh aspect, an eighth aspect of the present invention that relates to a hot-carrier resistance improvement technology is characterized by including a step of forming a buried channel region, a source region and a drain region, a step of forming a gate insulation layer after the step of forming the buried channel region, source region and drain region, and a step of exposing the gate insulation layer to an atmosphere containing water vapor at a temperature of 500xc2x0 C. or more after the step of forming the gate insulation layer in the semiconductor device that includes between a region in which the buried channel is formed and the source or drain region, a diffusion layer of nitrogen, phosphorus or arsenic at a maximum concentration that is 5xc3x971016 cmxe2x88x923 to 5xc3x971019 cmxe2x88x923.
In addition to any of the above first to eighth aspects, a ninth aspect of the present invention that relates to punch-through resistance improvement is characterized by including a step of forming a buried channel region, a source region and a drain region, a step of forming a gate insulation layer after the step of forming the buried channel region, source region and drain region, and a step of exposing the gate insulation layer to an atmosphere containing water vapor at a temperature of 500xc2x0 C. or more after the step of forming the gate insulation layer in the semiconductor device in which, located adjacently beneath the region in which the buried channel is formed, there is a P-type impurity diffusion region having an impurity concentration that is higher than an impurity concentration of the semiconductor substrate.
In addition to the ninth aspect, a tenth aspect of the present invention is characterized by including a step of forming a buried channel region a source region and a drain region, a step of forming a gate insulation layer after the step of forming the buried channel region, source region and drain region, and a step of exposing the gate insulation layer to an atmosphere containing water vapor at a temperature of 500xc2x0 C. or more after the step of forming the gate insulation layer in a semiconductor device having a high-concentration P-type impurity diffusion region located adjacently beneath the region in which the buried channel is formed that includes an aluminum or boron diffusion layer having a maximum impurity concentration of 1xc3x971017 cmxe2x88x923 to 1xc3x971019 cmxe2x88x923.
An eleventh aspect of the present invention relates to channel mobility improvement in a method of manufacturing a semiconductor device characterized by any of the first to tenth aspects, characterized by the gate insulation layer being formed by a thermal oxidation method using dry oxygen.